A. Field of the Invention
This application is related to the art of automated processing of numerical data, and more particularly to an improved method for implementing a multiplier/accumulator used in such processing.
B. Background Art
In the art of automated processing of numerical data, as typically carried out in a digital computer, a number of techniques have evolved over the past few decades for reducing the processing time for a given operation, or for accomplishing a given level of processing with lesser hardware complexity, or both. Among such techniques are the use of coding algorithms to effect an encoding of the terms of the multiplier for a given multiplication operation, which encoding results in a material diminution in the number of partial products to be added to find the resultant product of the multiplication, and thus a corresponding savings in the number of adder stages required to find the resultant sum of such partial products. Typical of such coding algorithms is the well-known Booth""s algorithm. Artisans in the computer processing arts continue, however, to seek means for further reducing the processing resources required to implement a given computer processing operation.
It is accordingly an object of the invention to provide an improved multiplier/accumulator which utilizes less processing resources than such devices which are known in the prior art. To that end, a method is provided for utilizing the processing resources of a multiplier-accumulator combination on a cooperative basis with the result that at least one adder stage in such a combination can be eliminated.